November 1993
Revised January 1999
7
4
AB
T1
6952 1
6
-Bi
t

Regist
ered
T
r
anscei
ver
wit
h
3-
ST
A
T
E
Output
s
© 1999 Fairchild Semiconductor Corporation DS011647.prf www.fairchildsemi.com
74ABT16952
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16952 is a 16-bit registered transceiver. Two 8-bit
back to back registers store data flowing in both directions
between two bidirectional buses. Separate clock, clock
enable and 3-STATE output enable signals are provided for
each register. The output pins are guaranteed to source 32
mA and to sink 64 mA.
Features
a73 Separate clock, clock enable and 3-STATE output
enable provided for each register
a73 A and B output sink capability of 64 mA source capability
of 32 mA
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Nondestructive hot insertion capability

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.
Pin Descriptions
Output Control
Register Function Table
(Applies to A or B Register)
H = HIGH Voltage Level Z = HIGH Impedance
L = LOW Voltage Level c17 = LOW-to-HIGH Transition
X = Immaterial NC = No Change
Connection Diagram
Pin Assignment for SSOP
Order Number Package Number Package Description
74ABT16952CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16952CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
A
0
–A
15
Data Register A Inputs/
B-Register 3-STATE Outputs
B
0
–B
15
Data Register B Inputs/
A-Register 3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
CEA
n
, CEB
n
Clock Enable
OEAB
n
, OEBA
n
Output Enable Inputs
OE Internal
Q
Output Function
H X Z Disable Outputs
L L L Enable Outputs
LH H
Inputs Internal
FunctionDCPCE Q
X X H NC Hold Data
L c17 L L Load Data
H c17 L H