October 1995 1/8
ST 486 DX ASIC CORE
Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE
PRELIMINARY DATA
a73 Fully Static 486 compatible core able to
operate from D.C to 120MHz
a73 Manufactured in a 0.35 micron five layer
metal HCMOS process
a73 8K byte unified instruction and data cache
with write back capability
a73 Parallel processing integral floating point unit,
with automatic power down mode
a73 Low Power system management modes
a73 Cell libraries for 2.2V and 3.3V supply with
5 V I/O interface capability
a73 2 - input NAND delay of 0.160 ns (typ) with
fanout = 2.
a73 Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
a73 High drive I/O; capability of sinking up to 48
mA with slew rate control, current spike sup-
pression and impedance matching.
a73 Generators to support SPRAM, DPRAM,
ROM and many other embedded functions.
a73 Fully independent power and ground configu-
rations for inputs, core and outputs.
a73 Programmable I/O ring capability up to 1000
pads.
a73 Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
a73 Active pull up and pull down devices.
a73 Buskeeper I/O functions.
a73 Oscillators for wide frequency spectrum.
a73 Broad range of 400 SSI cells.
a73 Design For Test includes LSSD macro library
option and IEEE 1149.1 JTAG Boundary
Scan architecture built in.
a73 Cadence based design system with inter-
faces from multiple workstations.
a73 Broad ceramic and plastic package range.
a73 Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts.
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Sea of Gates Standard Cells
Custom I/O Programm able
I/Oe.g RAMDAC
SVGA
CHIPSET / PCI
IDE / ISA
486 DX CORE
ROM
RAM
DPRAM
Figure 1. Example 486 DX Core ASIC