AFEDRI8201
器件描述:IF ADC Front End for AM/FM and HD Radios
文件大小:240.46KB,共22页
Sponsor by e络盟
器件资料摘要:
FEATURES
C0068 Interfaces To Texas Instruments DRIx50 HD
Radio Baseband Processors
C0068 12-Bit, 80MSPS ADC Reduces Noise and
Improves Sensitivity
C0068 Typical SNR of 102dB in 3kHz Bandwidth
C0068 Programmable Input Range For Optimum
Tuner Dynamic Range
C0068 Integrated Digital Downconverter (DDC)
− Quadrature Mixer, NCO, CIC Decimation
Filter, And FIR Filters
C0068 Mixer: 32-Bit Frequency and Phase
C0068 Decimation Ratio: 32 to 4096
C0068 User-Programmable FIR Filters with 16-Bit
Coefficients
C0068 12-Bit Auxiliary DAC
C0068 Code Composer Module for Easy Software
Generation
C0068 SPI Control Interface
APPLICATIONS
C0068 AM/FM and HD Radio Receivers
C0068 IF Receive Channels
C0068 Software Radios
C0068 Narrowband Receivers
DESCRIPTION
The AFEDRI8201 implements the receive channel analog
functions required for intermediate-frequency (IF)
sampled AM/FM and HD digital radio receivers. It is
designed to be used with TI’s DRIx50 digital baseband
processor. The AFEDRI8201 is programmed by the
DRIx50 for use in AM/FM and HD radio. The AFEDRI8201
oversamples the radio tuner IF output at speeds of up to
80MHz to reduce noise and improve dynamic range. The
radio tuner output IF is typically 10.7MHz for AM or FM as
well as 450kHz or 455kHz for AM, as desired. The
AFEDRI8201 then mixes, filters, and decimates the signal
to provide baseband I and Q output signals to the digital
baseband processor. The AFEDRI8201 also includes a
general-purpose 12-bit control digital-to-analog converter
(DAC) to provide a gain control signal or other analog
feedback to the tuner.
The DRIx50 digital baseband device writes control register
data as well as decimation filter coefficients to the
AFEDRI8201 through the industry-standard SPI control
interface. The baseband output signals are transported to
the DRIx50 through a general-purpose, high-speed serial
interface (TI’s Buffered Serial Ports, McBSP).
This unit uses 3.3V analog and 1.8V digital power
supplies. Typical power dissipation is 490mW. The digital
I/O lines can be powered by a 3.3V supply.
12−Bit
Pipeline
ADC
Auxiliary
DAC
Voltage
Reference
AUX
IFM
IFP
Quadrature
Mixer
NCO
CIC Filter FIR Filter 1 FIR Filter 2A
D
a
ta
I
n
te
r
f
ac
e
DOUT0
DOUT1
DFSO
DCLK
DIN
DFSI
FIR Filter 2B
N 2 2
2
REFM VCM REFP VGB
SPI Control
Interface
SCK MOSI MISO CS
Timing
Generator
PWD SYNC RESET
Clock
Interface
MCLK MCLKB
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AFEDRI8201
SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
IF ADC Front End for AM/FM and HD Radios
www.ti.com
Copyright 2003−2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.