TL/F/10205
54LS113
Dual
JK
Edge-Triggered
Flip-Flop
June 1989
54LS113
Dual JK Edge-Triggered Flip-Flop
General Description
The 54LS113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and data
may be entered. The logic level of the J and K inputs may
be changed when the clock pulse is HIGH and the bistable
will perform according to the Truth Table as long as mini-
mum setup and hold times are observed. Input data is trans-
ferred to the outputs on the falling edge of the clock pulse.
Connection Diagram
Dual-In-Line Package
TL/F/10205–1
Order Number 54LS113DMQB,
54LS113FMQB or 54LS113LMQB
See NS Package Number E20A, J14A or W14B
Logic Symbol
TL/F/10205–2
V
CC
e Pin 14
GND e Pin 7
Truth Table
Inputs Output
@
t
n
@
t
n
a 1
JK Q
LL Q
n
LH L
HL H
HH Q
n
t
n
eBit Time before Clock Pulse
t
n
a 1 e Bit Time after Clock Pulse
H e HIGH Voltage Level
L e LOW Voltage Level
Asynchronous Input:
Low input to S
D
sets Q to HIGH level
Set is independent of clock
Pin Names Description
J1, J2, K1, K2 Data Inputs
CP1, CP2 Clock Pulse Inputs (Active Falling Edge)
SD1, SD2 Direct Set Inputs (Active LOW)
Q1, Q2, Q1, Q2 Outputs
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.