© 2003 Fairchild Semiconductor Corporation DS500775 www.fairchildsemi.com
January 2003
Revised January 2003
1
00L
V
E
L1
1 3.
3V ECL
1:
2 Di
ff
erent
i
al
F
a
nout
Buff
er
100LVEL11
3.3V ECL 1:2 Differential Fanout Buffer
General Description
The 100LVEL11 is a low voltage 1:2 differential fanout
buffer. One differential input signal is fanned out to two
identical differential outputs. By supplying a constant refer-
ence level to one input pin a single ended input condition is
created.
With inputs Open or both inputs at V
EE
, the differential Q
outputs default LOW and Q outputs default HIGH.
The 100 series is temperature compensated.
Features
a73 Typical propagation delay of 330 ps
a73 Typical I
EE
of 24 mA
a73 Typical skew of 5 ps between outputs
a73 Internal pull-down resistors on D
a73 Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
a73 Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up tests
a73 Moisture Sensitivity Level 1
a73 ESD Performance:
Human Body Model > 2000V
Machine Model > 200V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Package Product
Package DescriptionNumber Code
Top Mark
100LVEL11M M08A KVL11 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100LVEL11M8
(Preliminary)
MA08D KV11 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name Description
Q
0
, Q
0
, Q
1
, Q
1
ECL Data Outputs
D, D ECL Data Inputs
V
CC
Positive Supply
V
EE
Negative Supply