TL/F/9833
DM74LS395
4-Bit
Shift
Register
with
TRI-STATE
Outputs
February 1992
DM74LS395
4-Bit Shift Register with TRI-STATE Outputs
General Description
The LS395 is a 4-bit shift register with TRI-STATE outputs
and can operate in either a synchronous parallel load or a
serial shift-right mode, as determined by the Select input. An
asynchronous active LOW Master Reset (MR) input over-
rides the synchronous operations and clears the register.
An active LOW Output Enable (OE) input controls the TRI-
STATE output buffers, but does not interfere with the other
operations. The fourth stage also has a conventional output
for linking purposes in multi-stage serial operations.
Features
Y
Shift right or parallel 4-bit register
Y
TRI-STATE outputs
Y
Input clamp diodes limit high speed termination effects
Y
Fully CMOS and TTL compatible
Connection Diagram
Dual-In-Line Package
TL/F/9833–1
Order Number DM74LS395WM or DM74LS395N
See NS Package Number M16B or N16E
Logic Symbol
TL/F/9833–2
V
CC
e Pin 16
GND e Pin 8
Mode Select Table
Operating Mode
Inputs
@
t
n
Outputs
@
t
na1
MR CP SD
S
P
n
O0 O1 O2 O3
Asynchronous Reset L X X X X L L L L
Shift, SET First Stage H K LH X HO0
n
O1
n
02
n
Shift, RESET First Stage H K LL X LO0
n
O1
n
02
n
Parallel Load H K HXPnP0P1 P2 P3
t
n
,t
na1
eTime before and after CP HIGH-to-LOW transition
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.