5476DMQB
器件描述：Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
器件厂商：NSC [National Semiconductor]
文件大小：108.45KB，共4页
Sponsor by e络盟器件资料摘要：
TL/F/6528
5476/DM5476/DM7476
Dual
Master-Slave
J-K
Flip-Flops
with
Clear,
Preset,
and
Complementary
Outputs
June 1989
5476/DM5476/DM7476
Dual Master-Slave J-K Flip-Flops with Clear,
Preset, and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data from
the J and K inputs is transferred to the master. While the
clock is high the J and K inputs are disabled. On the nega-
tive transition of the clock, the data from the master is trans-
ferred to the slave. The logic state of J and K inputs must
not be allowed to change while the clock is high. The data is
transfered to the outputs on the falling edge of the clock
pulse. A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs.
Features
Y
Alternate Military/Aerospace device (5476) is available.
Contact a National Semiconductor Sales Office/Distrib-
utor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6528–1
Order Number 5476DMQB, 5476FMQB,
DM5476J, DM5476W or DM7476N
See NS Package Number J16A, N16E or W16A
Function Table
Inputs Outputs
PR CLR CLK J K Q Q
LH XXXHL
HL XXXLH
LL H**
HH LLQ
0
Q
0
HH HL H L
HH LH L H
HH H H Toggle
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
e Positive pulse data. The J and K inputs must be held constant while
the clock is high. Data is transfered to the outputs on the falling edge of the
clock pulse.
* e This configuration is nonstable; that is, it will not persist when the preset
and/or clear inputs return to their inactive (high) level.
Q
0
e The output logic level before the indicated input conditions were es-
tablished.
Toggle e Each output changes to the complement of its previous level on
each complete active high level clock pulse.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
5476/DM5476/DM7476
Dual
Master-Slave
J-K
Flip-Flops
with
Clear,
Preset,
and
Complementary
Outputs
June 1989
5476/DM5476/DM7476
Dual Master-Slave J-K Flip-Flops with Clear,
Preset, and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data from
the J and K inputs is transferred to the master. While the
clock is high the J and K inputs are disabled. On the nega-
tive transition of the clock, the data from the master is trans-
ferred to the slave. The logic state of J and K inputs must
not be allowed to change while the clock is high. The data is
transfered to the outputs on the falling edge of the clock
pulse. A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs.
Features
Y
Alternate Military/Aerospace device (5476) is available.
Contact a National Semiconductor Sales Office/Distrib-
utor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6528–1
Order Number 5476DMQB, 5476FMQB,
DM5476J, DM5476W or DM7476N
See NS Package Number J16A, N16E or W16A
Function Table
Inputs Outputs
PR CLR CLK J K Q Q
LH XXXHL
HL XXXLH
LL H**
HH LLQ
0
Q
0
HH HL H L
HH LH L H
HH H H Toggle
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
e Positive pulse data. The J and K inputs must be held constant while
the clock is high. Data is transfered to the outputs on the falling edge of the
clock pulse.
* e This configuration is nonstable; that is, it will not persist when the preset
and/or clear inputs return to their inactive (high) level.
Q
0
e The output logic level before the indicated input conditions were es-
tablished.
Toggle e Each output changes to the complement of its previous level on
each complete active high level clock pulse.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.