1/10July 2001
a73 HIGH SPEED:
f
MAX
= 180MHz (TYP.) at V
CC
= 5V
a73 LOW POWER DISSIPATION:
I
CC
= 1µA(MAX.) at T
A
=25°C
a73 HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
a73 POWER DOWN PROTECTION ON INPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1G80 is an advanced high-speed CMOS
SINGLE POSITIVE EDGE TRIGGERED D-TYPE
FLIP-FLOP WITH INVERTED OUTPUT
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. it is
designed to operate from 2V to 5.5V, making this
device ideal for portable applications.
This D-Type flip-flop is controlled by a clock input
(CK). On the positive transition of the clock, the Q
output will be set to the logic inverted state that
was setup at the D input.
Following the hold time interval, data at the D input
can be changed without affecting the level at the
output. Power down protection is provided on
input and 0 to 7V can be accepted on input with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
It’s available in the commercial temperature
range. All inputs and output are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V1G80
SINGLE POSITIVE EDGE TRIGGERED
D-TYPE FLIP-FLOP

PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE T & R
SOT23-5L 74V1G80STR
SOT323-5L 74V1G80CTR
SOT323-5LSOT23-5L