74LVQ11MTR
器件描述：TRIPLE 3-INPUT AND GATE
器件厂商：STMICROELECTRONICS [STMicroelectronics]
厂商主页：http://www.st.com/
文件大小：157.26KB，共8页
Sponsor by e络盟器件资料摘要：
1/8July 2001
a73 HIGH SPEED:
t
PD
= 4.7ns (TYP.) at V
CC
= 3.3 V
a73 COMPATIBLE WITH TTL OUTPUTS
a73 LOW POWER DISSIPATION:
I
CC
= 2µA (MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
a73 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
a73 PCI BUS LEVELS GUARANTEED AT 24 mA
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 11
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ11 is a low voltage CMOS TRIPLE
3-INPUT AND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ11
TRIPLE 3-INPUT AND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVQ11M 74LVQ11MTR
TSSOP 74LVQ11TTR
TSSOPSOP
a73 HIGH SPEED:
t
PD
= 4.7ns (TYP.) at V
CC
= 3.3 V
a73 COMPATIBLE WITH TTL OUTPUTS
a73 LOW POWER DISSIPATION:
I
CC
= 2µA (MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
a73 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
a73 PCI BUS LEVELS GUARANTEED AT 24 mA
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 11
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ11 is a low voltage CMOS TRIPLE
3-INPUT AND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ11
TRIPLE 3-INPUT AND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVQ11M 74LVQ11MTR
TSSOP 74LVQ11TTR
TSSOPSOP