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厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

ADS5424IPJYR

器件描述:14 BIT, 105 MSPS ANALOG TO DIGITAL CONVERTER
器件厂商:TI [Texas Instruments]
厂商主页:http://www.ti.com/
文件大小:578.93KB,共25页
Sponsor by e络盟
器件资料摘要:
SLWS157A − JANUARY 2005 − REVISED MAY 2005
C0049C0052 C0066C0105C0116C0044 C0049C0048C0053 C0077C0083C0080C0083
C0065C0110C0097C0108C0111C0103C0262C0116C0111C0262C0068C0105C0103C0105C0116C0097C0108 C0067C0111C0110C0118C0101C0114C0116C0101C0114
C0065C0068C0083C0053C0052C0050C0052
FEATURES
C0068 14 Bit Resolution
C0068 105 MSPS Maximum Sample Rate
C0068 SNR = 74 dBc at 105 MSPS and 50-MHz IF
C0068 SFDR = 93 dBc at 105 MSPS and 50-MHz IF
C0068 2.2 V
pp
Differential Input Range
C0068 5 V Supply Operation
C0068 3.3 V CMOS Compatible Outputs
C0068 1.9 W Total Power Dissipation
C0068 2s Complement Output Format
C0068 On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
C0068 52 Pin HTQFP Package With Exposed
Heatsink
C0068 Pin Compatible to the AD6644/45
C0068 Industrial Temperature Range = −40C0053C to 85C0053C
APPLICATIONS
C0068 Single and Multichannel Digital Receivers
C0068 Base Station Infrastructure
C0068 Instrumentation
C0068 Video and Imaging
RELATED DEVICES
C0068 Clocking: CDC7005
C0068 Amplifiers: OPA695, THS4509
DESCRIPTION
The ADS5424 is a 14 bit 105 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing 3.3 V
CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the on-chip Track and Hold
(T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system
design. The ADS5424 has outstanding low noise and linearity, over input frequency. With only a 2.2 V
PP
input range,
simplifies the design of multicarrier applications, where the carriers are selected on the digital domain.
The ADS5424 is available in a 52 pin HTQFP with heatsink package and is pin compatible to the AD6645. The ADS5424
is built on state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full industrial
temperature range (−40°C to 85°C).
FUNCTIONAL BLOCK DIAGRAM
Reference
Timing
CLK+
OVR D[13:0]
CLK−
6
DMID DRY
VREF
A
IN
A
IN
TH1
5 5
Σ
DAC2ADC2
ADC3Σ
DAC1ADC1
A3
A1
TH2 TH3
C1
C2
AV
DD
DRV
DD
GND
Digital Error Correction
A2
+

+

PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
www.ti.com
www.ti.com
Copyright  2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
C0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046 C0080C0114C0111C0100C0117C0099C0116C0115
C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115 C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046
C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101 C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046