TL/F/6388
DM74LS126A
Quad
TRI-STATE
Buffer
September 1991
DM74LS126A Quad TRI-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-imped-
ance state to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
that two outputs will attempt to take a common bus to oppo-
site logic levels, the disable time is shorter than the enable
time of the outputs.
Connection Diagram
Dual-In-Line Package
TL/F/6388–1
Order Number DM74LS126AM or DM74LS126AN
See NS Package Number M14A or N14A
Function Table
Y e A
Inputs Output
AC Y
LH L
HH H
X L Hi-Z
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
Hi-Z e TRI-STATE (Outputs are disabled)
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.