C0083C0078C0055C0052C0067C0066C0051C0084C0051C0051C0056C0052
C0049C0048C0262C0066C0073C0084 C0070C0069C0084 C0066C0085C0083 C0083C0087C0073C0084C0067C0072
C0050C0046C0053C0262C0086C0047C0051C0046C0051C0262C0086 C0076C0079C0087C0262C0086C0079C0076C0084C0065C0071C0069 C0066C0085C0083 C0083C0087C0073C0084C0067C0072 C0087C0073C0084C0072 C0053C0262C0086C0262C0084C0079C0076C0069C0082C0065C0078C0084 C0076C0069C0086C0069C0076 C0083C0072C0073C0070C0084C0069C0082

SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C0068 Output Voltage Translation Tracks V
CC
C0068 Supports Mixed-Mode Signal Operation On
All Data I/O Ports
− 5-V Input Down To 3.3-V Output Level
Shift With 3.3-V V
CC
− 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V V
CC
C0068 5-V-Tolerant I/Os With Device Powered-Up
or Powered-Down
C0068 Bidirectional Data Flow, With Near-Zero
Propagation Delay
C0068 Low ON-State Resistance (r
on
)
Characteristics (r
on
= 5 Ω Typical)
C0068 Low Input/Output Capacitance Minimizes
Loading (C
io(OFF)
= 5 pF Typical)
C0068 Data and Control Inputs Provide
Undershoot Clamp Diodes
C0068 Low Power Consumption
(I
CC
= 40 µA Max)
C0068 V
CC
Operating Range From 2.3 V to 3.6 V
C0068 Data I/Os Support 0 to 5-V Signaling Levels
(For Example: 0.8-V, 1.2-V, 1.5-V, 1.8-V,
2.5-V, 3.3-V, 5-V)
C0068 Control Inputs Can Be Driven by TTL or
5-V/3.3-V/2.5-V CMOS Outputs
C0068 I
off
Supports Partial-Power-Down Mode
Operation
C0068 Latch-Up Performance Exceeds 250 mA Per
JESD 17
C0068 ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
C0068 Supports Digital Applications: Level
Translation, Memory Interleaving, Bus
Isolation
C0068 Ideal for Low-Power Portable Equipment
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
V
CC
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
description/ordering information
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube SN74CB3T3384DW
CB3T3384
Tape and reel SN74CB3T3384DWR
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel SN74CB3T3384DBQR CB3T3384
TSSOP − PW
Tube SN74CB3T3384PW
KS384
Tape and reel SN74CB3T3384PWR
TVSOP − DGV Tape and reel SN74CB3T3384DGVR
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright  2004, Texas Instruments IncorporatedC0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046
C0080C0114C0111C0100C0117C0099C0116C0115 C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115
C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046 C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101
C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.