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AIC-43C97
December 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
1 SCSI Host Interface Block
■ Dual Mode Ultra-2 I/O supporting Low
■ Voltage Differential (LVD) and Single
■ Ended SCSI Interfaces
– Ultra-2 (80 MB/s wide, 40 MB/s narrow) and
slower with LVD
– Ultra (40 MB/s wide, 20 MB/s narrow) and
slower with Single Ended
■ Supports Target and Initiator Modes
■ Programmable SCSI Sequencer for Target
Mode
– Automatic Command receipt with messages
– Automatic Disconnect and Reconnect
– Automatic Message
– Automatic Status
– Automatic parsing of frequently used SCSI
commands
– Reduced Microprocessor Overhead
– Auto Write & Auto Match operations
– Two active contexts to support command ex-
ecution pipelining or overlapping
■ Two 16-byte SCSI Control FIFO’s
■ 128-byte SCSI Data FIFO
■ Block or byte-based transfer counter
■ Odd-byte transfer support in byte mode
■ Stores configuration information for up to three
SCSI devices
■ Supports automatic SCAM selection and SCAM
transfer cycles
■ Selectable REQ/ACK noise Filtering
2 DMA Interface Block
■ “ATA DMA Master/Slave” mode:
– Supports 8/16-bit transfers with programma-
ble speeds up to 40 MB/s in 16-bit mode
■ “SCSI DMA” mode:
– Supports 8/16-bit transfers with programma-
ble speeds up to 100 MB/s in 16-bit asynchro-
nous/synchronous mode
■ “Generic” mode:
– Supports 8/16-bit transfers with programma-
ble speeds up to 40 MB/s in 16-bit mode
3 Microcontroller Interface Block
■ Selectable µP Style and Bus Mode
– Multiplexed or non-multiplexed
– Selectable strobing style (*RD & *WR, or E/
*DS & R/*W)
– 16-bit or 8-bit data (8-bit data only in non-mul-
tiplexed mode)
– Programmable CS and INT polarities
■ Supports wide variety of MPUs
– Intel 80C196xx
– Motorola 68HC11 & 68HC16
– NEC V852
– Hitachi SH-1 7034 & H8 3002
– Intel 80C186
4 Buffer Manager and Buffer RAM
■ 8KB RAM for buffering data and speed
matching between and Host DMA ports
■ Concurrent Buffer RAM access by Host and
DMA ports
■ MPU access of Buffer RAM when DMA port is
disabled
■ Parity protection on buffer data
■ Block or Byte based data flow control between
Host and DMA ports
5 Frequency Synthesizer
■ 960 MHz PLL for high resolution on selections
of HIFCLK and DIFCLK
DATA BRIEF
Automated, High-performance, Integrated, SCSI Protocol Controller
designed for SCSI-2/SCSI-3 embedded peripheral applications
Rev. 1
Figure 1. Package
Table 1. Order Codes
Part Number Package
AIC-43C97M/C TQFP144
TQFP144