1/8July 2001
a73 HIGH SPEED:
t
PD
= 8 ns (TYP.) at V
CC
= 3.3 V
a73 COMPATIBLE WITH TTL OUTPUTS
a73 LOW POWER DISSIPATION:
I
CC
= 2µA(MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
a73 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
a73 PCI BUS LEVELS GUARANTEED AT 24 mA
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ280 is a low voltage CMOS 9 BIT
PARITY GENERATOR fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (ΣODD and ΣEVEN). The nine
data inputs control the output conditions. When
the number of high level input is odd, ΣODD
output is kept high and ΣEVEN output low.
Conversely, when the number of high level is
even, ΣEVEN output is kept high and ΣODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ280
9 BIT PARITY GENERATOR

PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVQ280M 74LVQ280MTR
TSSOP 74LVQ280TTR
TSSOPSOP