AZ100EL31
器件资料摘要：
AZ10EL31
AZ100EL31
ECL/PECL D Flip-Flop with Set and Reset
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
• 475ps Propagation Delay
• 2.8GHz Toggle Frequency
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor
MC10EL31 & MC100EL31
DESCRIPTION
The AZ10/100EL31 is a master-slave D flip-flop with set and reset. The device is functionally equivalent to the
E131 device with higher performance capabilities. With propagation delays and output transition times significantly
faster than the E131, the EL31 is ideally suited for those applications that require the ultimate in AC performance.
Both set and reset inputs are asynchronous, level triggered signals. Data enters the master section of the flip-
flop when the clock is LOW. When the clock transitions from LOW to HIGH, the data in the master section
transfers into the slave section and through to the outputs.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
8
5
6
7
4
3
2
1
V
CC
D
V
EE
S
Q
Q
R
S
D
R
Flip Flop
CLK
PACKAGE AVAILABILITY
PACKAGE PART NO. MARKING
SOIC 8 AZ10EL31D AZM10EL31
SOIC 8 T&R AZ10EL31DR1 AZM10EL31
SOIC 8 T&R AZ10EL31DR2 AZM10EL31
SOIC 8 AZ100EL31D AZM100EL31
SOIC 8 T&R AZ100EL31DR1 AZM100EL31
SOIC 8 T&R AZ100EL31DR2 AZM100EL31
TSSOP 8 AZ10EL31T AZTEL31
TSSOP 8 T&R AZ10EL31TR1 AZTEL31
TSSOP 8 T&R AZ10EL31TR2 AZTEL31
TSSOP 8 AZ100EL31T AZHEL31
TSSOP 8 T&R AZ100EL31TR1 AZHEL31
TSSOP 8 T&R AZ100EL31TR2 AZHEL31
TRUTH TABLE
D
S*
R*
CLK
Q
Q¯
L L L Z L H
H L L Z H L
X H L X H L
X L H X L H
X H H X Undef Undef
Z = LOW to HIGH Transition
* Pins will default low when left open
PIN DESCRIPTION
PIN FUNCTION
S Set Input
D Data Input
R Reset Input
CLK Clock Input
Q, Q¯ Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
AZ100EL31
ECL/PECL D Flip-Flop with Set and Reset
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
• 475ps Propagation Delay
• 2.8GHz Toggle Frequency
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor
MC10EL31 & MC100EL31
DESCRIPTION
The AZ10/100EL31 is a master-slave D flip-flop with set and reset. The device is functionally equivalent to the
E131 device with higher performance capabilities. With propagation delays and output transition times significantly
faster than the E131, the EL31 is ideally suited for those applications that require the ultimate in AC performance.
Both set and reset inputs are asynchronous, level triggered signals. Data enters the master section of the flip-
flop when the clock is LOW. When the clock transitions from LOW to HIGH, the data in the master section
transfers into the slave section and through to the outputs.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
8
5
6
7
4
3
2
1
V
CC
D
V
EE
S
Q
Q
R
S
D
R
Flip Flop
CLK
PACKAGE AVAILABILITY
PACKAGE PART NO. MARKING
SOIC 8 AZ10EL31D AZM10EL31
SOIC 8 T&R AZ10EL31DR1 AZM10EL31
SOIC 8 T&R AZ10EL31DR2 AZM10EL31
SOIC 8 AZ100EL31D AZM100EL31
SOIC 8 T&R AZ100EL31DR1 AZM100EL31
SOIC 8 T&R AZ100EL31DR2 AZM100EL31
TSSOP 8 AZ10EL31T AZTEL31
TSSOP 8 T&R AZ10EL31TR1 AZTEL31
TSSOP 8 T&R AZ10EL31TR2 AZTEL31
TSSOP 8 AZ100EL31T AZHEL31
TSSOP 8 T&R AZ100EL31TR1 AZHEL31
TSSOP 8 T&R AZ100EL31TR2 AZHEL31
TRUTH TABLE
D
S*
R*
CLK
Q
Q¯
L L L Z L H
H L L Z H L
X H L X H L
X L H X L H
X H H X Undef Undef
Z = LOW to HIGH Transition
* Pins will default low when left open
PIN DESCRIPTION
PIN FUNCTION
S Set Input
D Data Input
R Reset Input
CLK Clock Input
Q, Q¯ Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply