Publication# 11419 Rev. D Amendment /0
Issue Date: May 1995
2-10
Advanced
Micro
Devices
Am27C64
64 Kilobit (8,192 x 8-Bit) CMOS EPROM
FINAL
DISTINCTIVE CHARACTERISTICS
a73 Fast access time
— 45 ns
a73 Low power consumption
— 20 m A typical CMOS standby current
a73 JEDEC-approved pinout
a73 Single +5 V power supply
a73 – 10% power supply tolerance available
a73 100% Flashrite
TM
programming
— Typical programming time of 1 second
a73 Latch-up protected to 100 mA from –1 V to
VCC + 1 V
a73 High noise immunity
a73 Versatile features for simple interfacing
— Both CMOS and TTL input/output
compatibility
— Two line control functions
a73 Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C64 is a 64-Kbit ultraviolet erasable program-
mable read-only memory. It is organized as 8K words by
8 bits per word, operates from a single +5 V supply, has
a static standby mode, and features fast single address
location programming. Products are available in win-
dowed ceramic DIP packages as well as plastic one
time programmable (OTP) PDIP, and PLCC packages.
Typically, any byte can be accessed in less than 45 ns,
allowing operation with high-performance microproces-
sors without any WAIT states. The Am27C64 offers
separate Output Enable (OE) and Chip Enable (CE)
controls, thus eliminating bus contention in a multiple
bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 80 mW in active mode, and 100 m W in
standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
or at random. The Am27C64 supports AMD’s Flashrite
programming algorithm (100 m s pulses) resulting in a
typical programming time of 1 second.
BLOCK DIAGRAM
VCC
VSS
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
CE
OE
Output
Buffers
Y
Gating
65,538
Bit Cell
Matrix
A0–A12
Address
Inputs
Data Outputs
DQ0–DQ7
11419D-1
VPP
PGM