1/9July 2001
a73 HIGH SPEED: t
PD
= 5ns (TYP.) at V
CC
= 5V
a73 LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
a73 COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
a73 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT125 is an advanced high-speed CMOS
QUAD BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
This device require the 3-STATE control input G to
be set high to place the output in high impedance
state.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT125
QUAD BUS BUFFERS (3-STATE)

PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
DIP 74ACT125B
SOP 74ACT125M 74ACT125MTR
TSSOP 74ACT125TTR
TSSOPDIP SOP