74AC11651
器件描述：OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
器件厂商：TI [Texas Instruments]
厂商主页：http://www.ti.com/
文件大小：142.45KB，共9页
Sponsor by e络盟器件资料摘要：
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
Copyright 1993, Texas Instruments Incorporated
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Independent Registers and Enables for A
and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• Flow-Through Architecture Optimizes PCB
Layout
• Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted
CMOS) 1-m m Process
• 500-mA Typical Latch-Up Immunity at
125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and
OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and
a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that
can be performed with the 74AC11651.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.
The 74AC11651 is characterized for operation from –40°C to 85°C.
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OEAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
OEBA
CLKAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CLKBA
SBA
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
Copyright 1993, Texas Instruments Incorporated
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Independent Registers and Enables for A
and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• Flow-Through Architecture Optimizes PCB
Layout
• Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted
CMOS) 1-m m Process
• 500-mA Typical Latch-Up Immunity at
125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and
OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and
a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that
can be performed with the 74AC11651.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.
The 74AC11651 is characterized for operation from –40°C to 85°C.
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OEAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
OEBA
CLKAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CLKBA
SBA
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.