54AC11109, 74AC11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS450 – MARCH 1987 – REVISED APRIL 1993
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright  1993, Texas Instruments Incorporated
2–1
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted
CMOS) 1-m m Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• ESD Protection Exceeds 2000 V,
MIL STD-883C Method 3015
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs

description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When preset and clear are inactive
(high), data at the J and K inputs meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by grounding K and
tying J high. They also can perform as D-type
flip-flops by tying the J and K inputs together.
The 54AC11109 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC11109 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS OUTPUTS
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
L LXXXH
†
H
†
H H ↑ LLLH
H H ↑ H L Toggle
H H ↑ LHQ
0
Q
0
H H ↑ HHHL
H H L X X Q
0
Q
0
†
This configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to its inactive (high) level.
54AC11109 ...J PACKAGE
74AC11109 ...D OR N PACKAGE
(TOP VIEW)
54AC11109 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2CLK
1CLK
1K
1J
1CLR
V
CC
2CLR
2J
2K
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1J NC
2Q 2Q
2CLR
1Q
GND
NC
V1CLR
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.