EEPROM
AS58C1001
Austin Semiconductor, Inc.
AS58C1001
Rev. 4.0 3/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
For more products and information
please visit our web site at
www.austinsemiconductor.com
128K x 8 EEPROM
EEPROM Memory
AVAILABLE AS MILITARY
SPECIFICATIONS
l SMD 5962-38267
l MIL-STD-883
FEATURES
l High speed: 150, 200, and 250ns
l Data Retention: 10 Years
l Low power dissipation, active current (20mW/MHz (TYP)),
standby current (100µW(MAX))
l Single +5V (+10%) power supply
l Data Polling and Ready/Busy Signals
l Erase/Write Endurance (10,000 cycles in a page mode)
l Software Data protection Algorithm
l Data Protection Circuitry during power on/off
l Hardware Data Protection with RES pin
l Automatic Programming:
Automatic Page Write: 10ms (MAX)
128 Byte page size
OPTIONS MARKINGS
l Timing
150ns access -15
200ns access -20
250ns access -25
l Packages
Ceramic Flat Pack F No. 306
Radiation Shielded Ceramic FP* SF No. 305
Ceramic SOJ DCJ No. 508
l Operating Temperature Ranges
-Military (-55
o
C to +125
o
C) XT
-Industrial (-40
o
C to +85
o
C) IT
*NOTE: Package lid is connected to ground (Vss).
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS58C1001 is a 1 Megabit CMOS
Electrically Erasable Programmable Read Only Memory (EEPROM)
organized as 131, 072 x 8 bits. The AS58C1001 is capable or in
system electrical Byte and Page reprogrammability.
The AS58C1001 achieves high speed access, low power consump-
tion, and a high level of reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology and
CMOS process and circuitry technology.
This device has a 128-Byte Page Programming function to make its
erase and write operations faster. The AS58C1001 features Data
Polling and a Ready/Busy signal to indicate completion of erase and
programming operations.
This EEPROM provides several levels of data protection. Hard-
ware data protection is provided with the RES pin, in addition to noise
protection on the WE signal and write inhibit during power on and off.
Software data protection is implemented using JEDEC Optional Stan-
dard algorithm.
The AS58C1001 is designed for high reliability in the most de-
manding applications. Data retention is specified for 10 years and
erase/write endurance is guaranteed to a minimum of 10,000 cycles in
the Page Mode.
PIN ASSIGNMENT
(Top View)
32-Pin CFP (F & SF), 32-Pin CSOJ (DCJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RDY/BUSY\
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
I/O 1
I/O 2
Vss
Vcc
A15
RES\
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
PIN NAME FUNCTION
A0 to A16 Address input
I/O0 to I/O7 Data input/output
OE\ Output enable
CE\ Chip enable
WE\ Write enable
Vcc Power supply
Vss Ground
RDY/Busy\ Ready busy
RES\ Reset