3D7428
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7428 – LOW NOISE)

FEATURES PACKAGES

• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Leading- and trailing-edge accuracy
• Programmable via serial or parallel interface
• Increment range: 0.25 through 20.0ns
• Delay tolerance: 0.5% (See Table 1)
• Supply current: 3mA typical
• Temperature stability: ±1.5% max (-40C to 85C)
• Vdd stability: ±0.5% max (4.75V to 5.25V)



FUNCTIONAL DESCRIPTION

The 3D7428 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:

T
i,nom
= T
inh
+ i * T
inc


where i is the programmed address, T
inc
is the delay increment (equal
to the device dash number), and T
inh
is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.

The all-CMOS 3D7428 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount
16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.

TABLE 1: PART NUMBER SPECIFICATIONS
data
delay
devices, inc.

3
PIN DESCRIPTIONS

IN Signal Input
OUT Signal Output
MD Mode Select
AE Address Enable
P0-P7 Parallel Data Input
SC Serial Clock
SI Serial Data Input
SO Serial Data Output
VDD +5 Volts
GND Ground


1
2
3
4
8
7
6
5
IN
SO
AE
GND
VDD
OUT
SC
SI
3D7428Z-xx SOIC
143SO/P0 MD

16
15
13
12
11
10
9
1
2
4
5
6
7
8
IN
AE
P1
P2
P3
P4
GND
VDD
OUT
P7
P6
SC
P5
SI
3D7428-xx DIP

1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
AE
SO/P0
P1
P2
P3
P4
GND
VDD
OUT
MD
P7
P6
SC
P5
SI
3D7428S-xx SOL
For mechanical dimensions, click here.
For package marking details, click here.

PART DELAYS AND TOLERANCES INPUT RESTRICTIONS
NUMBER
Inherent
Delay (ns)
Delay
Range (ns)
Delay
Step (ns)
Rec’d Max
Frequency
Absolute Max
Frequency
Rec’d Min
Pulse Width
Absolute Min
Pulse Width
3D7428-0.25 10.5 ± 2.0 63.75 ± 0.4 0.25 ± 0.12 6.25 MHz 77 MHz 80.0 ns 6.5 ns
3D7428-0.5 10.5 ± 2.0 127.5 ± 0.5 0.50 ± 0.25 3.12 MHz 45 MHz 160.0 ns 11.0 ns
3D7428-1 10.5 ± 2.0 255.0 ± 1.0 1.00 ± 0.50 1.56 MHz 22 MHz 320.0 ns 22.0 ns
3D7428-1.5 10.5 ± 2.0 382.5 ± 1.5 1.50 ± 0.75 1.04 MHz 15 MHz 480.0 ns 33.0 ns
3D7428-2 10.5 ± 2.0 510.0 ± 2.0 2.00 ± 1.00 781 KHz 11 MHz 640.0 ns 44.0 ns
3D7428-2.5 10.5 ± 2.5 637.5 ± 2.5 2.50 ± 1.25 625 KHz 9.0 MHz 800.0 ns 55.0 ns
3D7428-4 13.0 ± 4.0 1020 ± 3.2 4.00 ± 2.00 390 KHz 5.6 MHz 1280.0 ns 88.0 ns
3D7428-5 15.0 ± 5.0 1275 ± 4.0 5.00 ± 2.50 312 KHz 4.5 MHz 1600.0 ns 110.0 ns
3D7428-7.5 20.0 ± 7.5 1912.5 ± 6.0 7.50 ± 3.75 208 KHz 3.0 MHz 2400.0 ns 165.0 ns
3D7428-10 23.5 ± 10 2550 ± 8.0 10.0 ± 5.00 156 KHz 2.2 MHz 3200.0 ns 220.0 ns
3D7428-15 33.0 ± 15 3825 ± 12 15.0 ± 9.00 104 KHz 1.5 MHz 4800.0 ns 330.0 ns
3D7428-20 42.0 ± 20 5100 ± 16 20.0 ± 12.0 78 KHz 1.1 MHz 6400.0 ns 440.0 ns

NOTES: Any delay increment between 0.25 and 20 ns not shown is also available as standard.
See application notes section for more details 2004 Data Delay Devices

Doc #03003 DATA DELAY DEVICES, INC. 1
11/1/04 3 Mt. Prospect Ave. Clifton, NJ 07013