128K x 8 High-Speed CMOS EPROM
fax id: 3023
CY27H010

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 1994 – Revised March 1997
1CY 27H0 10
Features
• CMOS for optimum speed/power
• High speed
—t
AA
= 25 ns max. (commercial)
—t
AA
= 35 ns max. (military)
• Low power
— 275 mW max.
— Less than 85 mW when deselected
• Byte-wide memory organization
• 100% reprogrammable in thewindowed package
• EPROM technology
• Capable of withstanding >2001V static discharge
• Available in
— 32-pin PLCC
— 32-pin TSOP-I
— 32-pin, 600-mil plastic or hermetic DIP
— 32-pin hermetic LCC
Functional Description
The CY27H010 is a high-performance, 1-megabit CMOS
EPROM organized in 128 Kbytes. It is available in indus-
try-standard 32-pin, 600-mil DIP, LCC, PLCC, and TSOP-I
packages. These devices offer high-density storage com-
bined with 40-MHz performance. The CY27H010 is available
in windowed and opaque packages. Windowed packages al-
low the device to be erased with UV light for 100% re-
programmability.
The CY27H010 is equipped with a power-down chip enable
(CE) input and output enable (OE). When CE is deasserted,
the device powers down to a low-power stand-by mode. The
OE pin three-states the outputs without putting the device into
stand-by mode. While CE offers lower power, OE provides a
more rapid transition to and from three-stated outputs.
The memory cells utilize proven EPROM floating-gate technol-
ogy and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the supervoltage and
low programming current allows for gang programming. The
device allows for each memory location to be tested 100%,
because each location is written to, erased, and repeatedly
exercised prior to encapsulation. Each device is also tested
for AC performance to guarantee that the product will meet DC
and AC specification limits after customer programming.
The CY27H010 is read by asserting both the CE and the OE
inputs. The contents of the memory location selected by the
address on inputs A
16
–A
0
will appear at the outputs O
7
–O
0
.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
DIP
12
13
29
32
31
30
16
15
17
18
GND
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
14
V
CC
PGM
A
13
A
8
A
9
O
7
O
6
O
5
O
4
A
2
V
PP
O
0
O
1
O
2
CE
OE
A
10
O
3
A
1
A
0
A
11
NC
H010–1
H010–2
12
O
0
314
5
6
7
8
9
10
321 30
13
14151617
26
25
24
23
22
21
11
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
10
A
13
A
8
A
9
OE
CE
O
7
Top View
LCC/PLCC
A
14
A
11
181920
27
28
29
32
H010–3
A
0
PROGRAMMABLE
ARRAY
O
0
O
1
O
7
O
2
O
4
O
3
O
5
O
6
ADDRESS
DECODER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
8
A
7
MULTIPLEXER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
OUTPUT ENABLE
DECODER
CE
OE
POWER DOWN