C0083C0077C0074C0051C0050C0048C0067C0052C0048C0044 C0084C0077C0080C0051C0050C0048C0067C0052C0048
C0068C0073C0071C0073C0084C0065C0076 C0083C0073C0071C0078C0065C0076 C0080C0082C0079C0067C0069C0083C0083C0079C0082C0083
SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001
1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
C0068 SMJ: QML Processing to MIL–PRF–38535
C0068 SM: Standard Processing
C0068 TMP: Commercial Level Processing TAB
C0068 Operating Temperature Ranges:
– Military (M) –55°C to 125°C
– Special (S) –55°C to 100°C
– Commercial (C) –25°C to 85°C
– Commercial (L) 0°C to 70°C
C0068 Highest Performance Floating-Point Digital
Signal Processor (DSP)
– C40-60:
33-ns Instruction Cycle Time:
60 MFLOPS, 30 MIPS, 330 MOPS,
384 MBps
– C40-50:
40-ns Instruction Cycle Time:
50 MFLOPS, 25 MIPS, 275 MOPS,
320 MBps
– C40-40:
50-ns Instruction Cycle Time:
40 MFLOPS, 20 MIPS, 220 MOPS,
256 MBps
C0068 Six Communications Ports
C0068 6-Channel Direct Memory Access (DMA)
Coprocessor
C0068 Single-Cycle Conversion to and From
IEEE-745 Floating-Point Format
C0068 Single Cycle 1/x, 1/
C0068 Source-Code Compatible With SMJ320C30
C0068 Validated Ada Compiler
C0068 Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
C0068 12 40-Bit Registers, 8 Auxiliary Registers,
14 Control Registers, and 2 Timers
C0068 IEEE Standard 1149.1
†
Test-Access Port
(JTAG)
C0068 Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
– High Port-Data Rate of 100 MBytes/s
(Each Bus)
– 16G-Byte Continuous
Program/Data/Peripheral Address Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-, Data-, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
C0068 Packaging:
– 325-Pin Ceramic Grid Array (GF Suffix)
– 352-Lead Ceramic Quad Flatpack
(HFH Suffix)
– 324-Pad JEDEC-Standard TAB Frame
C0068 Fabricated Using Enhanced Performance
Implanted CMOS (EPIC) Technology by
Texas Instruments (TI)
C0068 Separate Internal Program, Data, and DMA
Coprocessor Buses for Support of Massive
Concurrent Input/Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance
C0068 On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache
– 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Bootloader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories Over Any One of the
Communications Ports

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046
C0080C0114C0111C0100C0117C0099C0116C0115 C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115
C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046 C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101
C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046
Copyright  2001, Texas Instruments Incorporated
x
C0504
†
IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
EPIC and TI are trademarks of Texas Instruments Incorporated.
C0079C0110 C0112C0114C0111C0100C0117C0099C0116C0115 C0099C0111C0109C0112C0108C0105C0097C0110C0116 C0116C0111 C0077C0073C0076C0262C0080C0082C0070C0262C0051C0056C0053C0051C0053C0044 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115 C0097C0114C0101 C0116C0101C0115C0116C0101C0100
C0117C0110C0108C0101C0115C0115 C0111C0116C0104C0101C0114C0119C0105C0115C0101 C0110C0111C0116C0101C0100C0046 C0079C0110 C0097C0108C0108 C0111C0116C0104C0101C0114 C0112C0114C0111C0100C0117C0099C0116C0115C0044 C0112C0114C0111C0100C0117C0099C0116C0105C0111C0110
C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101 C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046