1. General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2. Features
a73 Wide supply voltage range from 1.65 V to 5.5 V
a73 5 V tolerant inputs for interfacing with 5 V logic
a73 High noise immunity
a73 Complies with JEDEC standard:
a78 JESD8-7 (1.65 V to 1.95 V)
a78 JESD8-5 (2.3 V to 2.7 V)
a78 JESD8B/JESD36 (2.7 V to 3.6 V).
a73 ±24 mA output drive (V
CC
= 3.0 V)
a73 ESD protection:
a78 HBM EIA/JESD22-A114-B exceeds 2000 V
a78 MM EIA/JESD22-A115-A exceeds 200 V.
a73 CMOS low power consumption
a73 Latch-up performance exceeds 250 mA
a73 Direct interface with TTL levels
a73 Inputs accept voltages up to 5 V
a73 Multiple package options
a73 Specified from −40 °Cto+85°C and −40 °C to +125 °C.
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 — 18 October 2004 Product data sheet