1. General description
The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device.
The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A
HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW
level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
2. Features
a73 Symmetrical output impedance
a73 High noise immunity
a73 ESD protection:
a78 HBM EIA/JESD22-A114-A exceeds 2000 V
a78 MM EIA/JESD22-A115-A exceeds 200 V
a78 CDM EIA/JESD22-C101 exceeds 1000 V.
a73 Low power dissipation
a73 Balanced propagation delays
a73 SOT505-2 and SOT765-1 package
a73 Specified from −40 °C to +85 °C and from −40 °C to +125 °C.
3. Quick reference data
74AHC2G241; 74AHCT2G241
Dual buffer/line driver; 3-state
Rev. 01 — 10 March 2004 Product data sheet
Table 1: Quick reference data
GND = 0 V; T
amb
=25°C; t
r
=t
f
≤ 3.0 ns.
Symbol Parameter Conditions Min Typ Max Unit
Type 74AHC2G241
t
PHL
, t
PLH
propagation delay nA to nY C
L
= 15 pF; V
CC
= 5 V - 3.4 5.5 ns
t
PZH
, t
PZL
enable time1OE to 1Y C
L
= 15 pF; V
CC
= 5 V - 3.6 5.1 ns
enable time 2OE to 2Y C
L
= 15 pF; V
CC
= 5 V - 3.6 5.6 ns
t
PHZ
, t
PLZ
disable time1OE to 1Y C
L
= 15 pF; V
CC
= 5 V - 4.1 6.8 ns
disable time 2OE to 2Y C
L
= 15 pF; V
CC
= 5 V - 4.3 6.8 ns
C
I
input capacitance - 1.5 10 pF
C
PD
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz
[1] [2]
-10-pF