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厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

5962-0051001QXA

器件描述:FIXED POINT SIGNAL PROCESSOR
器件厂商:TI [Texas Instruments]
厂商主页:http://www.ti.com/
文件大小:1224.75KB,共10页
Sponsor by e络盟
器件资料摘要:
C0083C0077C0074C0051C0050C0048C0067C0054C0050C0048C0051
C0070C0073C0088C0069C0068C0262C0080C0079C0073C0078C0084 C0068C0073C0071C0073C0084C0065C0076 C0083C0073C0071C0078C0065C0076 C0080C0082C0079C0067C0069C0083C0083C0079C0082
SGUS033 – FEBRUARY 2002
1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
C0068 High-Performance Fixed-Point Digital
Signal Processor (DSP) – SMJ320C62x
– 5-ns Instruction Cycle Time
– 200-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1600 Million Instructions Per Second
(MIPS)
C0068 429-Pin Ball Grid Array (BGA) Package
(GLP Suffix)
C0068 VelociTI Advanced Very-Long-Instruction-
Word (VLIW) C62x DSP Core
– Eight Highly Independent Functional
Units:
– Six Arithmetic Logic Units (ALUs)
(32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Result)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
C0068 Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
C0068 7M-Bit On-Chip SRAM
– 3M-Bit Internal Program/Cache
(96K 32-Bit Instructions)
– 4M-Bit Dual-Access Internal Data
(512K Bytes)
– Organized as Two 256K-Byte Blocks
for Improved Concurrency
C0068 Flexible Phase-Locked-Loop (PLL) Clock
Generator
C0068 32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
– 52M-Byte Addressable External Memory
Space
C0068 Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
C0068 32-Bit Expansion Bus
– Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
– Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
C0068 Three Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral Interface (SPI)
Compatible (Motorola)
C0068 Two 32-Bit General-Purpose Timers
C0068 IEEE-1149.1 (JTAG

)
Boundary-Scan-Compatible
C0068 0.15-µm/5-Level Metal Process
– CMOS Technology
C0068 3.3-V I/Os, 1.5-V Internal

C0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046
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C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046 C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101
C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SMJ320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright  2002, Texas Instruments Incorporated
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