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FEATURES
APPLICATIONS
DESCRIPTION
12−Bit
ADC
PLL
S/H Serializer
1X ADCLK
6X ADCLK
IN1P
ADCLK
IN1N
OUT1P
OUT1N
12−Bit
ADCS/H Serializer
IN2P
IN2N
OUT2P
OUT2N
12−Bit
ADCS/H Serializer
IN3P
IN3N
OUT3P
OUT3N
LCLKP
LCLKN
ADCLKP
ADCLKN
12−Bit
ADCS/H Serializer
IN4P
IN4N
OUT4P
OUT4N
Reference
R
E
F
TINT/EXT
V
C
M
R
E
F
B
Registers
S
C
L
K
S
D
A
T
A
C
S
Control
R
E
S
E
T
P
D
ADS5240
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
4-Channel, 12-Bit, 40MSPS ADC
with Serial LVDS Interface
An integrated phase lock loop multiplies the incoming
ADC sampling clock by a factor of 12. This 12x clock• Maximum Sample Rate: 40MSPS
is used in the process of serializing the data output• 12-Bit Resolution
from each channel. The 12x clock is also used to
generate a 1x and a 6x clock, both of which are• No Missing Codes
transmitted as LVDS clock outputs. The 6x clock is• Power Dissipation: 607mW
denoted by the differential pair LCLK P and LCLK N ,• CMOS Technology
while the 1x clock is denoted by ADCLK P and
• Simultaneous Sample-and-Hold ADCLK N . The word output of each ADC channel can
be transmitted either as MSB or LSB first. The bit• 70.5dBFS SNR at 10MHz IF
coinciding with the rising edge of the 1x clock output• Internal and External References
is the first bit of the word. Data is to be latched by the
• 3.3V Digital/Analog Supply receiver on both the rising and falling edges of the 6x
clock.• Serialized LVDS Outputs
• Integrated Frame and Bit Patterns The ADS5240 provides internal references, or can
optionally be driven with external references. Best• MSB and LSB First Modes
performance can be achieved through the internal• Option to Double LVDS Clock Output Currents
reference mode.
• Pin- and Format-Compatible Family The device is available in an HTQFP-64 PowerPAD
• HTQFP-64 PowerPAD ™ Package package and is specified over a -40 ° C to +85 ° C
operating range.
• Portable Ultrasound Systems
• Tape Drives
• Test Equipment
• Optical Networking
The ADS5240 is a high-performance, 4-channel,
40MSPS analog-to-digital converter (ADC). Internal
references are provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
(low-voltage differential signaling) outputs reduce the
number of interface lines and package size.
RELATED PRODUCTS
RESOLUTION SAMPLE RATE
MODEL (BITS) (MSPS) CHANNELS
ADS5242 (1) 12 65 4
(1) Available Q1 2005.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.