1/9April 2004
a73 HIGH SPEED:
f
MAX
= 180MHz (TYP.) at V
CC
=5V
t
CK-Q
= 3.9ns (TYP.) at V
CC
=5V
a73 LOW POWER DISSIPATION:
I
CC
=1µA(MAX.) at T
A
=25°C
a73 COMPATIBLE WITH TTL OUTPUTS:
V
IH
=2V(MIN),V
IL
=0.8V(MAX)
a73 POWER DOWN PROTECTION ON INPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
=8mA(MIN)atV
CC
=4.5V
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1T79 is an advanced high-speed CMOS
SINGLE POSITIVE EDGE TRIGGERED D-TYPE
FLIP-FLOP fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is designed to operate from 4.5V to
5.5V, making this device ideal for portable
applications.
This D-Type flip-flop is controlled by a clock input
(CK). On the positive transition of the clock, the Q
output will be set to the logic state that was setup
at the D input.
Following the hold time interval, data at the D input
can be changed without affecting the level at the
output. Power down protection is provided on
inputs and 0 to 7V can be accepted on inputs with
no regard to the supply voltage. This device can
be used to interface 5V to 3V systems.
It’s available in the commercial and extended
temperature range.
All inputs and output are equipped with protection
circuits against static discharge, giving them ESD
immunity and transient excess voltage.
74V1T79
SINGLE POSITIVE EDGE TRIGGERED
D-TYPE FLIP-FLOP
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE T & R
SOT23-5L 74V1T79STR
SOT323-5L 74V1T79CTR
SOT323-5LSOT23-5L