© 2005 Fairchild Semiconductor Corporation DS011605 www.fairchildsemi.com
May 1993
Revised February 2005
7
4
L
VX86
Low V
o
l
t
age
Q
u
ad 2-
Inpu
t
Exclusi
ve-
O
R

Gate
74LVX86
Low Voltage Quad 2-Input Exclusive-OR Gate
General Description
The LVX86 contains four 2-input exclusive-OR gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
Features
a73 Input voltage level translation from 5V to 3V
a73 Ideal for low power/low noise 3.3V applications
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Package Description
Number
74LVX86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX86SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX86MTCX_NL
(Note 1)
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names Description
A
0
–A
3
Inputs
B
0
–B
3
Inputs
O
0
–O
3
Outputs