3379B–FLASH–9/03
4-megabit
Top Boot,
Bottom
Partitioned
Firmware Hub
and Low-Pin
Count Flash
Memory
AT49LH00B4
Other Sectors
– Five General-purpose Input (GPI) Pins for System Design Flexibility
– Identification (ID) Pins for Multiple Device Selection
– Sector Locking Registers for Individual Sector Read and Write Protection
A/A Mux Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Facilitates Fast In-System or Out-of-System Programming
Single Voltage Operation
– 3.0V to 3.6V Supply Voltage for Read and Write Operations
Industry-Standard Package Options
– 32-lead PLCC
– 40-lead TSOP
Description
The AT49LH00B4 is a Flash memory device designed for use in PC and notebook
BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec-
ification, providing support for both FWH and LPC memory read and write cycles. The
device can also automatically detect the memory cycle type to allow the AT49LH00B4
to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
Pin Configurations
PLCC
Note: [ ] Designates A/A Mux Interface.
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0/LAD0
IC [IC]
GND
NC
NC
VCC
INIT [OE]
FWH4/LFRAME [WE]
RES [RDY/BSY]
RES [I/O7]
4 3 2 1
32 31 30
14 15 16 17 18 19 20
[I/O1] FWH1/LAD1 [I/O2] FWH2/LAD2
GND
[I/O3] FWH3/LAD3
[I/O4] RES [I/O5] RES [I/O6] RES
GPI2 [A8] GPI3 [A9] RST [RST] NC VCC CLK [R/C] GPI4 [A10]
TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
[IC] IC
NC
NC
NC
NC
[A10] GPI4
NC
[R/C] CLK
VCC
NC
[RST] RST
NC
NC
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
GND
VCC
FWH4/LFRAME [WE]
INIT [OE]
RES [RDY/BSY]
RES [I/O7]
RES [I/O6]
RES [I/O5]
RES [I/O4]
VCC
GND
GND
FWH3/LAD3 [I/O3]
FWH2/LAD2 [I/O2]
FWH1/LAD1 [I/O1]
FWH0/LAD0 [I/O0]
ID0 [A0]
ID1 [A1]
ID2 [A2]
ID3 [A3]
Features
Complies with Intel
®
Low-Pin Count (LPC) Inte
– Supports both Firmware Hub (FWH) and LPC M
Auto-detection of FWH and LPC Memory Cycle
– Can Be Used as FWH for Intel 8xx, E7xxx, a
– Can Be Used as LPC Flash for Non-Intel Chips
Top Boot with Bottom Partitioned Memory Arra
– 64-Kbyte Top Boot Sector, Six 64-Kbyte Se
16-Kbyte Sector, Two 8-Kbyte Sectors
– Or Memory Array Can Be Divided Into Eigh
Two Configurable Interfaces
– FWH/LPC Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interfa
Manufacturing
FWH/LPC Interface
– Operates with the 33 MHz PCI Bus Clock
– 5-signal Communication Interface Supporting By
– Two Hardware Write Protect Pins: TBL for T
rface Specification Revision 1.1
emory Read and Write Cycles
s
nd E8xxx Series Chipsets
ets
y for Efficient Vital Data Storage
ctors, One 32-Kbyte Sector, One
t Uniform 64-Kbyte Sectors for Erasing
ce for Programming during
te Reads and Writes
op Boot Sector and WP for All
1