© 2003 Fairchild Semiconductor Corporation DS500230 www.fairchildsemi.com
November 1999
Revised August 2003
7
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VC
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44
Low V
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74VCXH16244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
General Description
The VCXH16244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The VCXH16244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74VCXH16244 is designed for low voltage (1.2V to
3.6V) V
CC
applications with output capability up to 3.6V.
The 74VCXH16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.2V to 3.6V V
CC
supply operation
a73 3.6V tolerant control inputs and outputs
a73 Bushold on data inputs eliminating the need for external
pull-up/pull-down resistors
a73 t
PD
2.5 ns max for 3.0V to 3.6V V
CC
a73 Static Drive (I
OH
/I
OL
)
±24 mA @ 3.0V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
a73 Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)

Ordering Code:
Note 1: Ordering Code “G” indicates Tray.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74VCXH16244G
(Note 1)(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCXH16244MTD
(Note 2)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide