1/13December 2001
a73 HIGH SPEED:
f
MAX
= 170 MHz (TYP.) at V
CC
= 5V
a73 LOW POWER DISSIPATION:
I
CC
= 1 µA (MAX.) at T
A
=25°C
a73 HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
a73 POWER DOWN PROTECTION ON INPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
a73 FUNCTION COMPATIBLE WITH
74 SERIES 74
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2G74 is an advanced high-speed CMOS
SINGLE D-TYPE FLIP FLOP WITH PRESET
AND CLEAR fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
tecnology.
A signal on the D INPUT is transfered to the Q and
Q OUTPUTS during the positive going transition
of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V2G74
SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR

PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE T & R
SOT23-8L 74V2G70STR
SOT323-8L 74V2G70CTR
SOT23-8L SOT323-8L