ADS8364
器件描述:250kHz, 16-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS
文件大小:393.49KB,共22页
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器件资料摘要:
250kHz, 16-Bit, 6-Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
a71 6 INPUT CHANNELS
a71 FULLY DIFFERENTIAL INPUTS
a71 6 INDEPENDENT 16-BIT ADC
a71 4µs TOTAL THROUGHPUT PER CHANNEL
a71 TESTED NO MISSING CODES TO 14 BITS
a71 BUFFERED REFERENCE INPUTS
a71 LOW POWER: 450mW
a71 TQFP-64 PACKAGE
APPLICATIONS
a71 MOTOR CONTROL
a71 MULTI-AXIS POSITIONING SYSTEMS
a71 3-PHASE POWER CONTROL
DESCRIPTION
The ADS8364 includes six, 16-bit, 250KHz ADCs (Analog-to-
Digital converters) with 6 fully differential input channels
grouped into two pairs for high-speed simultaneous signal
acquisition. Inputs to the sample-and-hold amplifiers are fully
differential and are maintained differential to the input of the
ADC. This provides excellent common-mode rejection of
80dB at 50KHz that is important in high-noise environments.
The ADS8364 offers a flexible high-speed parallel interface
with a direct address mode, a cycle, and a FIFO mode. The
output data for each channel is available as a 16-bit word.
ADS8364
SBAS219B – JUNE 2002 – REVISED JULY 2004
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Copyright © 2002-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AD
S836
4
®
Interface
Conversion
and
Control
FIFO
Register
6x
EOC
FD
CS
WR
RD
Data
Input/Output
16
RESET
BYTE
CLK
CH A0–
CH A0+
CH A1–
CH A1+
SAR
CDAC
S/H
Amp
Comp
CDAC
Comp
S/H
Amp
CH B0–
CH B0+
HOLDA
CH B1–
CH B1+
SAR
CDAC
S/H
Amp
Comp
CDAC
Comp
S/H
Amp
CH C0–
CH C0+
CH C1–
CH C1+
REF
IN
REF
OUT
SAR
CDAC
S/H
Amp
Comp
CDAC
Comp
S/H
Amp
HOLDB
HOLDC
ADD
A2
A1
A0
Internal
2.5V
Reference
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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