© 2003 Fairchild Semiconductor Corporation DS500776 www.fairchildsemi.com
January 2003
Revised February 2003
1
00L
V
E
L1
6 3.
3V ECL
Dif
f
er
enti
al
Recei
ver
100LVEL16
3.3V ECL Differential Receiver
General Description
The 100LVEL16 is a low voltage differential receiver that
contains an internally supplied voltage source, V
BB
. When
used in a single ended input condition the unused input
must be tied to V
BB
. When operating in this mode use a
0.01 µF capacitor to decouple V
BB
and V
CC
and also limit
the current sinking or sourcing capability to 0.5mA. When
V
BB
is not used it should be left open.
With inputs open the differential Q outputs default LOW
and Q outputs default HIGH.
The 100 series is temperature compensated.
Features
a73 Typical propagation delay of 300 ps
a73 Typical I
EE
of 17 mA
a73 Internal pull-down resistors on D
a73 Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
a73 Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
a73 Moisture Sensitivity Level 1
a73 ESD Performance:
Human Body Model > 2000V
Machine Model > 150V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Product
Package DescriptionPackage Code
Number Top Mark
100LVEL16M M08A KVL16 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100LVEL16M8
(Preliminary)
MA08D KV16 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name Description
Q, Q ECL Data Outputs
D, D ECL Data Inputs
V
BB
Reference Voltage
V
CC
Positive Supply
V
EE
Negative Supply
NC No Connect