AD9954
器件描述：400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
器件厂商：AD [Analog Devices]
文件大小：1027.31KB，共36页
Sponsor by e络盟器件资料摘要：
400 MSPS 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9954
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
Programmable phase/amplitude dithering
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
Ultrahigh speed analog comparator
Automatic linear and nonlinear frequency sweeping
capability
4 frequency/phase offset profiles
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Integrated 1024 word × 32-bit RAM
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Automotive radar
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY
ACCUMULATOR
STATIC RAM
1024 × 32
COS(X)
CONTROL REGISTERS
OSCILLATOR/BUFFER
COMPARATOR
SYNC
ENABLE
I/O UPDATE
DAC_R
SET
DDS CORE
PHASE
OFFSET
PHASE
ACCUMULATOR
Z
–1
Z
–1
IOUT
IOUT
OSK
PWRDWNCTL
COMP_OUT
COMP_IN
COMP_IN
REFCLK
REFCLK
CRYSTAL OUT I/O PORTPS<1:0>
RAM DATA
<31:18>
DDS
CLOCK
RAM
DATA
DE
LTA FRE
Q
UE
NCY
TUNING WORD
FRE
Q
UE
NCY
TUNING WORD
RAM DATA DDS
CLOCK
DE
LTA FRE
Q
UE
NCY
RAMP
RATE
PH
A
S
E
ACUMULATOR
R
ESET
DAC
MUX
SYSTEM
CLOCK
SYSTEM
CLOCK
SYNC_IN
SYNC_CLK
RESET
TIMING AND CONTROL LOGIC
4×–20×
CLOCK
MULTIPLIER
÷ 4
AD9954
3232
32
14
14
14
32
R
A
M
A
D
D
R
E
S
S
10
RAM CONTROL
3
19 14
0
32
32
M
U
X
M
U
X
M
U
X
03374-0-001
θ
Figure 1. 48-LeadTQFP/EP
Direct Digital Synthesizer
AD9954
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
Programmable phase/amplitude dithering
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
Ultrahigh speed analog comparator
Automatic linear and nonlinear frequency sweeping
capability
4 frequency/phase offset profiles
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Integrated 1024 word × 32-bit RAM
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Automotive radar
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY
ACCUMULATOR
STATIC RAM
1024 × 32
COS(X)
CONTROL REGISTERS
OSCILLATOR/BUFFER
COMPARATOR
SYNC
ENABLE
I/O UPDATE
DAC_R
SET
DDS CORE
PHASE
OFFSET
PHASE
ACCUMULATOR
Z
–1
Z
–1
IOUT
IOUT
OSK
PWRDWNCTL
COMP_OUT
COMP_IN
COMP_IN
REFCLK
REFCLK
CRYSTAL OUT I/O PORTPS<1:0>
RAM DATA
<31:18>
DDS
CLOCK
RAM
DATA
DE
LTA FRE
Q
UE
NCY
TUNING WORD
FRE
Q
UE
NCY
TUNING WORD
RAM DATA DDS
CLOCK
DE
LTA FRE
Q
UE
NCY
RAMP
RATE
PH
A
S
E
ACUMULATOR
R
ESET
DAC
MUX
SYSTEM
CLOCK
SYSTEM
CLOCK
SYNC_IN
SYNC_CLK
RESET
TIMING AND CONTROL LOGIC
4×–20×
CLOCK
MULTIPLIER
÷ 4
AD9954
3232
32
14
14
14
32
R
A
M
A
D
D
R
E
S
S
10
RAM CONTROL
3
19 14
0
32
32
M
U
X
M
U
X
M
U
X
03374-0-001
θ
Figure 1. 48-LeadTQFP/EP