G97
REV. PrF (6/04)
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3MSPS,12-/10-/8-Bit
ADCs in 6-Lead TSOT
Preliminary Technical Data
AD7276/AD7277/AD7278
PRELIMINARY TECHNICAL DATA
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fast Throughput Rate: 3MSPS
Specified for V
DD
of 2.35 V to 3.6V
Low Power:
13.5 mW max at 3MSPS with 3V Supplies
TBD mW typ at 1.5MSPS with 3V Supplies
Wide Input Bandwidth:
70dB SNR at 1MHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI
TM
/QSPI
TM
/MICROWIRE
TM
/DSP Compatible
Power Down Mode: 1µA max
6-Lead TSOT Package
8-lead MSOP Package
AD7476 and AD7476A pin compatible
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors
PRODUCT HIGHLIGHTS
1. 3MSPS ADCs in a 6-lead TSOT package.
2. AD7476/77/78 and AD7476A/77A/78A pin compatible.
3. High Throughput with Low Power Consumption.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. This allows the average
power consumption to be reduced when a power-down
mode is used while not converting. The part also
features a power-down mode to maximize power effi-
ciency at lower throughput rates. Current consumption is
1 µA max when in Power-Down mode.
5. Reference derived from the power supply.
6. No Pipeline Delay.
The parts feature a standard successive-approximation
ADC with accurate control of the sampling instant via a
G67G83 input and once-off conversion control.
GENERAL DESCRIPTION
The AD7276/AD7277/AD7278 are 12-bit, 10-bit and 8-
bit, high speed, low power, successive-approximation
ADCs respectively. The parts operate from a single 2.35V
to 3.6 V power supply and feature throughput rates up to 3
MSPS. The parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of TBD MHz.
The conversion process and data acquisition are controlled
using G67G83 and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of G67G83 and the conversion is
also initiated at this point. There are no pipeline delays
associated with the part.
The AD7276/AD7277/AD7278 use advanced design
techniques to achieve very low power dissipation at high
throughput rates.
The reference for the part is taken internally from V
DD.
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to V
DD
. The
conversion rate is determined by the SCLK.
T/H
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
V
DD
V
IN
GND
SCLK
SDATA
c38c54
AD7276/AD7277/AD7278