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AD6635
4-Channel, 80 MSPS WCDMA
Receive Signal Processor (RSP)
FUNCTIONAL BLOCK DIAGRAM
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
INB[13:0]
EXPB[2:0]
LIB-A
LIB-B
IENB
INC[13:0]
EXPC[2:0]
IENC
LIB-A
LIB-B
IND[13:0]
EXPD[2:0]
LID-A
LID-B
IEND
SYNCA
SYNCB
SYNCC
SYNCD
EXTERNAL
SYNC.
CIRCUIT
I
N
P
U
T
M
A
T
R
I
X
I
N
P
U
T
M
A
T
R
I
X
NCO
NCO
NCO
NCO
NCO
NCO
NCO
NCO
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
CLK
RSP
CLK
RAM
COEFFICIENT
FILTER
CHANNEL 0
RAM
COEFFICIENT
FILTER
CHANNEL 1
RAM
COEFFICIENT
FILTER
CHANNEL 2
RAM
COEFFICIENT
FILTER
CHANNEL 3
RAM
COEFFICIENT
FILTER
CHANNEL 4
RAM
COEFFICIENT
FILTER
CHANNEL 5
RAM
COEFFICIENT
FILTER
CHANNEL 6
RAM
COEFFICIENT
FILTER
CHANNEL 7
BUILT-IN (BIST)
SELF-TEST CIRCUITRY
TO A AND B
OUTPUT
PORTS
TO A AND B
OUTPUT
PORTS
TO A AND B
OUTPUT
PORTS
TO A AND B
OUTPUT
PORTS
CH B INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
CH A INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
CH C INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
CH D INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
TO C AND D
OUTPUT
PORTS
TO C AND D
OUTPUT
PORTS
TO C AND D
OUTPUT
PORTS
TO C AND D
OUTPUT
PORTS
MICROPORT OR SERIAL
PORT CONTROL
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
RCF OUTPUTS
CHANNELS 4, 5, 6, 7
RCF OUTPUTS
CHANNELS 4, 5, 6, 7
PORT A
LINK PORT
OR
PARALLEL
PORT
CH A AND B
OUTPUT MUX
CIRCUITRY
PORT B
LINK PORT
OR
PARALLEL
PORT
PORT C
8-BIT DSP
LINK PORT
OR
16-BIT
PARALLEL
OUTPUT
PORT D
8-BIT DSP
LINK PORT
OR
16-BIT
PARALLEL
OUTPUT
CH C AND D
OUTPUT MUX
CIRCUITRY
FEATURES
Four 80 MSPS Wideband Inputs (14 Linear Bits Plus 3 RSSI)
4 Real Input Ports/2 Complex Input Ports
Processes 4 Wideband Channels (UMTS or cdma2000
1x) or 8 GSM/EDGE, IS136 Channels
8 Independent Digital Receivers in a Single Package
Four 16-Bit Parallel Output Ports and Four 8-Bit Link Ports
4 Programmable Digital AGC Loops with 96 dB Range
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
4 Interpolating Half-Band Filters
Flexible Control for Multicarrier and Phased Array
Programmable Attenuator Control for Clip Prevention and
External Gain Ranging via Level Indicator
3.3 V I/O, 2.5 V CMOS Core
User Configurable Built-in Self Test (BIST) Capability
APPLICATIONS
Multicarrier, Multimode Digital Receivers
GSM, IS136, EDGE, PHS, IS95, UMTS, cdma2000
Micro and Pico Cell Systems, Software Radios
Wireless Local Loop
Smart Antenna Systems
In-Building Wireless Telephony