REV. A
a
ADN2811
OC-48/OC-48 FEC Clock and Data Recovery IC
with Integrated Limiting Amp
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
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FEATURES
Meets SONET Requirements for Jitter Transfer/
Generation/Tolerance
Quantizer Sensitivity: 4 mV Typ
Adjustable Slice Level: H11550100 mV
1.9 GHz Minimum Bandwidth
Patented Clock Recovery Architecture
Loss of Signal Detect Range: 3 mV to 15 mV
Single Reference Clock Frequency for Both Native
SONET and 15/14 (7%) Wrapper Rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK LVPECL/LVDS/LVCMOS/LVTTL
Compatible Inputs (LVPECL/LVDS Only at 155.52 MHz)
19.44 MHz Oscillator On-Chip to Be Used with
External Crystal
Loss of Lock Indicator
Loopback Mode for High Speed Test Data
Output Squelch and Bypass Features
Single-Supply Operation: 3.3 V
Low Power: 540 mW Typical
7 mm H11547 7 mm 48-Lead LFCSP
APPLICATIONS
SONET OC-48, SDH STM-16, and 15/14 FEC
WDM Transponders
Regenerators/Repeaters
Test Equipment
Backplane Applications
FUNCTIONAL BLOCK DIAGRAM
LEVEL
DETECT
DATA
RETIMING
FRACTIONAL
DIVIDER
FREQUENCY
LOCK
DETECTOR
LOOP
FILTER
PHASE
SHIFTER
PHASE
DET.
VCO
XTAL
OSC
LOOP
FILTER
QUANTIZER
/n
ADN2811
SLICEP/N VCC VEE
CF1 CF2
LOL
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
RATECLKOUTP/NDATAOUTP/NSDOUT
THRADJ
VREF
NIN
PIN
2
2
22
2
PRODUCT DESCRIPTION
The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for –40H11543C to +85H11543C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gb/s and 2.66 Gb/s
digital wrapper rate is supported by the ADN2811, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at
the output.
The ADN2811 is available in a compact 7 mm × 7 mm 48-lead
chip scale package.