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厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

AT25128A

器件描述:SPI Serial Extended Temperature EEPROMs
器件厂商:ATMEL [ATMEL Corporation]
厂商主页:http://www.atmel.com/
文件大小:390.76KB,共18页
Sponsor by e络盟
器件资料摘要:
5088C–SEEPR–11/04
SPI Serial
Extended
Temperature
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
Features
• Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
Medium-voltage and Standard-voltage Operation
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
Extended Temperature Range −40°C to +125°C
5 MHz Clock Rate
64-byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >100 Years
8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and automotive applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate erase cycle is required before write.
Table 1. Pin Configurations
Pin Name Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
NC No Connect
DC Don't Connect
1
2
3
4
8
7
6
5
8-Lead PDIP
1
2
3
4
8
7
6
5
8-lead SOIC
1
2
3
4
8
7
6
5
8-lead TSSOP
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
VCC
HOLD
SCK
SI
1