© 1999 Fairchild Semiconductor Corporation DS009581 www.fairchildsemi.com
March 1988
Revised August 1999
7
4F651
•
74F652

T
r
anscei
vers/
Regist
ers
74F651 • 74F652
Transceivers/Registers
General Description
These devices consist of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function.
Features
a73 Independent registers for A and B buses
a73 Multiplexed real-time and stored data
a73 Choice of non-inverting and inverting data paths
74F651 inverting
74F652 non-inverting

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number Package Number Package Description
74F651SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F651SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide