TL/F/10177
54LS160A/DM74LS160A,
54LS162A/DM74LS162A
Synchronous
Presettable
BCD
Decade
Counters
May 1992
54LS160A/DM74LS160A, 54LS162A/DM74LS162A
Synchronous Presettable BCD Decade Counters
General Description
The ’LS160 and ’LS162 are high speed synchronous dec-
ade counters operating in the BCD (8421) sequence. They
are synchronously presettable for application in programma-
ble dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming synchro-
nous multistage counters. The ’LS160 has an asynchronous
Master Reset input that overrides all other inputs and forces
the outputs LOW. The ’LS162 has a Synchronous Reset
input that overrides counting and parallel loading and allows
all outputs to be simultaneously reset on the rising edge of
the clock.
Features
Y
Synchronous counting and loading
Y
High speed synchronous expansion
Y
Typical count rate of 35 MHz
Y
Fully edge triggered
Connection Diagram
Dual-In-Line Package
TL/F/10177–1
*MR for ’LS160
*SR for ’LS162
Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB,
54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM,
DM74LS160AN, DM74LS162AM or DM74LS162AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Pin
Description
Names
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input (Active Rising Edge)
MR (’160) Asynchronous Master Reset
Input (Active LOW)
SR (’162) Synchronous Reset
Input (Active LOW)
P0–P3 Parallel Data Inputs
PE Parallel Enable Input
(Active LOW)
Q0–Q3 Flip-Flop Outputs
TC Terminal Count Output
Logic Symbol
TL/F/10177–2
V
CC
e Pin 16 *MR for ’LS160
GND e Pin 8 *SR for ’LS162
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.