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厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

5962-9866101QXA

器件描述:FLOATING - POINT DIGITAL SIGNAL PROCESSOR
器件厂商:TI [Texas Instruments]
厂商主页:http://www.ti.com/
文件大小:894.04KB,共63页
Sponsor by e络盟
器件资料摘要:
C0083C0077C0074C0051C0050C0048C0067C0054C0055C0048C0049
C0070C0076C0079C0065C0084C0073C0078C0071C0262C0080C0079C0073C0078C0084 C0068C0073C0071C0073C0084C0065C0076 C0083C0073C0071C0078C0065C0076 C0080C0082C0079C0067C0069C0083C0083C0079C0082


SGUS030B – APRIL 2000 – REVISED MAY 2001
1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
C0068 Highest Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
– 7-, 6-ns Instruction Cycle Time
– 140-, 167-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– Up to 1 GFLOPS Performance
– Pin-Compatible With ’C6201 Fixed-Point
DSP
C0068 SMJ: QML Processing to MIL-PRF-38535
C0068 SM: Standard Processing
C0068 Operating Temperature Ranges
– Extended (W) –55°C to 115°C
– Extended (S) –40°C to 90°C
C0068 VelociTI Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
– Eight Highly Independent Functional
Units:
– Four ALUs (Floating- and Fixed-Point)
– Two ALUs (Fixed-Point)
– Two Multipliers (Floating- and
Fixed-Point)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
C0068 Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions
– Hardware Support for IEEE
Double-Precision Instructions
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
C0068 1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data
(64K Bytes)
C0068 32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
C0068 Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
C0068 16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
C0068 Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
C0068 Two 32-Bit General-Purpose Timers
C0068 Flexible Phase-Locked-Loop (PLL) Clock
Generator
C0068 IEEE-1149.1 (JTAG

)
Boundary-Scan-Compatible
C0068 429-Pin Ceramic Ball Grid Array (CBGA)
Package (GLP Suffix)
C0068 0.18-µm/5-Level Metal Process
– CMOS Technology
C0068 3.3-V I/Os, 1.9-V Internal

Copyright  2001, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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