C0065C0068C0083C0053C0052C0049C0051C0045C0049C0049
SLWS156 − MARCH 2004
C0083C0073C0078C0071C0076C0069 C0049C0049C0262C0066C0073C0084C0044 C0054C0053C0262C0077C0083C0080C0083 C0072C0073C0071C0072 C0073C0070 C0083C0065C0077C0080C0076C0073C0078C0071
C0065C0078C0065C0076C0079C0071C0262C0084C0079C0262C0068C0073C0071C0073C0084C0065C0076 C0067C0079C0078C0086C0069C0082C0084C0069C0082

FEATURES
C0068 11-Bit Resolution
C0068 65-MSPS Maximum Sample Rate
C0068 2-V
pp
Differential Input Range
C0068 3.3-V Single Supply Operation
C0068 1.8-V to 3.3-V Output Supply
C0068 400-mW Total Power Dissipation
C0068 Two’s Complement Output Format
C0068 On-Chip S/H and Duty Cycle Adjust Circuit
C0068 Internal or External Reference
C0068 63.3-dBFS SNR and 72.9-dBc SFDR at
65 MSPS and 220-MHz Input
C0068 Power-Down Mode
C0068 Single-Ended or Differential Clock
C0068 1-GHz −3-dB Input Bandwidth
C0068 48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size)
APPLICATIONS
C0068 Cellular Base Transceiver Station Receive
Channel
− High IF Sampling Applications
− CDMA: IS-95, UMTS, CDMA1X
− TDMA: GSM, IS-136, EDGE/UWC-136
− Wireless Local Loop
− Wideband Baseband Receivers
DESCRIPTION
The ADS5413−11 is a low power, 11-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from
a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and
low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit
allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous
sampling. The device can also be clocked with single ended or differential clock, without change in performance. The
internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the
application.
The device is specified over full temperature range (−40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
Digital Error Correction
7 Stages
Internal
Reference
Generator
1.8 V
1.25 V
DCA
CML
VBG
CLK
AGNDD[0:10]
AVDD
A/DΣ
VREFB
CLKC
2 2
OVDD
OGND
S/H
VREFT
2.25 V
Σ
D/AA/D
2
VINP
VINN
Gain
Stage
Gain
Stage
Σ
2
Gain
Stage
Flash
PWD
REF SEL
DCA
D/AA/D
D/AA/D
CommsADC is a trademark of Texas Instruments.
C0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046 C0080C0114C0111C0100C0117C0099C0116C0115
C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115 C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046
C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101 C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright  2004, Texas Instruments Incorporated