14/12/10-Bit, 1200 MSPS
D/A Converters
Preliminary Technical Data AD9736/AD9735/AD9734
FEATURES
• 1.8/3.3 V Dual Supply Operation
• AD9736 SFDR > 53 dBc to fOUT = 600 MHz
• AD9736 IMD > 65 dBc to fOUT = 600 MHz
• AD9736 DNL = ± 1.0 LSB
• AD9736 INL = ± 2.0 LSB
• Low power: 380 mW (IOUTFS = 20 mA; fOUT = 330 MHz)
• LVDS data interface with on-chip 100 Ω terminations
• Analog Output: Adjustable 10-30mA (RL=25 Ω to 50 Ω)
• On-Chip 1.2 V Reference
• 160 pin BGA Package
APPLICATIONS
• Instrumentation
• Automatic Test Equipment
• RADAR
• Avionics
• Wideband Communications Systems:
Point-to-Point Wireless
LMDS
PA Linearization

PRODUCT DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multi-carrier generation up to their Nyquist frequency.
The AD9736 is the 14 bit member of the family, while the AD9735
and the AD9734 are the 12 and 10 bit members, respectively. They
include a serial peripheral interface (SPI) port that provides for
programming many internal parameters and also enables read-back
of status registers. They use a reduced specification LVDS interface
to minimize data interface noise that may degrade performance.
The output current can be programmed over a range of 10mA to
30mA. The AD9736 family is manufactured on a 0.18µm CMOS
process and operates from 1.8V and 3.3V supplies for a total power
consumption of 380mW in bypass mode. It is supplied in a 160 pin
BGA package for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
LV
D
S
R
e
c
e
i
v
er
S
y
n
c
hr
on
i
z
at
i
o
n
Bandgap
DATACLK_IN+
DATACLK_IN-
DB[13:0]-
DB[13:0]+
Clock Distribution
SPI
14,12,10-Bit
DAC
IOUTA
IOUTB
2X
SDO
SDI
SCLK
CSB
LV
D
S
Dr
i
v
e
r
Controller
Reference
Current
CL
K
-
CL
K
+
RS
E
T
VR
EF
RE
S
E
T
DATACLK_OUT+
DATACLK_OUT-
S1 S2 S3
C1
C2
C3
C2 C1 S1
S3
S2
C3
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
Ultra-low Noise and Intermodulation Distortion (IMD) enable
high quality synthesis of wideband signals at intermediate
frequencies up to 600 MHz.
Double Data Rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
Direct pin programmability of basic functions or SPI port access
for complete control of all AD9736 family functions.
Manufactured on a CMOS process, the AD9736 family uses a
proprietary switching technique that enhances dynamic
performance.
The current output(s) of the AD9736 family can be easily
configured for various single-ended or differential circuit
topologies.



Rev. PrJ 9/7/2004
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