1/8June 2001
a73 HIGH SPEED: t
PD
= 4.3 ns (TYP.) at V
CC
= 5V
a73 LOW POWER DISSIPATION:
I
CC
= 2 µA (MAX.) at T
A
=25°C
a73 HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
a73 POWER DOWN PROTECTION ON INPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN)
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 08
a73 IMPROVED LATCH-UP IMMUNITY
a73 LOW NOISE: V
OLP
= 0.8V (MAX.)
DESCRIPTION
The 74VHC08 is an advanced high-speed CMOS
QUAD 2-INPUT AND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 2 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC08
QUAD 2-INPUT AND GATE

PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74VHC08M 74VHC08MTR
TSSOP 74VHC08TTR
TSSOPSOP