Preliminary
© 2002 Fairchild Semiconductor Corporation DS500774 www.fairchildsemi.com
September 2002
Revised September 2002
1
00EL
T
23
5V Dual Dif
f
e
r
ent
i
al

PECL to TTL T
r
ansl
ator

(
P
rel
i
mi
nary)
100ELT23
5V Dual Differential PECL to TTL Translator (Preliminary)
General Description
The 100ELT23 is a dual differential PECL to TTL translator
operating from a single +5V supply.
The dual gate design of the 100ELT23 makes it ideal for
applications which require the translation of a clock and a
data signal.
The 100 series is temperature compensated.
Features
a73 Typical propagation delay of 3.5 ns
a73 TTL output drive: I
OH
= 24 mA; I
OL
= −3 mA
a73 Flow through pinout
a73 Q Output will default to a LOW with the inputs left Open
a73 Internal pull-down resistors on inputs
a73 Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
a73 Typical I
CCH
of 23 mA, I
CCL
of 26 mA
a73 Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
a73 Moisture Sensitivity Level TBD
a73 ESD Performance:
Human Body Model > TBD
Machine Model > TBD

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Product
Package DescriptionPackage Code
Number Top Mark
100ELT23M M08A KLT23 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100ELT23M8
(Preliminary)
MA08D KT23 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name Description
D
0
, D
0
, D
1
, D
1
PECL Differential Inputs
Q
0
, Q
1
TTL Outputs
V
CC
Positive Supply
GND Ground