ADC12DL040
器件描述：Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter
器件厂商：NSC [National Semiconductor]
文件大小：1091.11KB，共26页
Sponsor by e络盟器件资料摘要：
ADC12DL040
Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter
General Description
The ADC12DL040 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 40 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize die size and power con-
sumption while providing excellent dynamic performance
and a 250 MHz Full Power Bandwidth. Operating on a single
+3.0V power supply, the ADC12DL040 achieves 11.1 effec-
tive bits at nyquist and consumes just 210 mW at 40 MSPS,
including the reference current. The Power Down feature
reduces power consumption to 36 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
REF
with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADC’s are available on a single multiplexed 12-bit
bus or on separate buses. Duty cycle stabilization and output
data format are selectable using a quad state function pin.
The output data can be set for offset binary or two’s comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL040 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evalua-
tion process.
Features
n Single +3.0V supply operation
n Internal sample-and-hold
n Internal reference
n Outputs 2.4V to 3.6V compatible
n Power down mode
n On-chip reference
n Duty Cycle Stabilizer
n Multiplexed Output Mode
Key Specifications
n Resolution 12 Bits
n DNL ±0.3 LSB (typ)
n SNR (f
IN
= 10 MHz) 69 dB (typ)
n SFDR (f
IN
= 10 MHz) 85 dB (typ)
n Data Latency 7 Clock Cycles
n Power Consumption
n -- Operating 210 mW (typ)
n -- Power Down Mode 36 mW (typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
Connection Diagram
20100201
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
February 2005
ADC12DL040
Dual
12-Bit,
40
MSPS,
3V
,
210mW
A/D
Converter
© 2005 National Semiconductor Corporation DS201002 www.national.com
Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter
General Description
The ADC12DL040 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 40 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize die size and power con-
sumption while providing excellent dynamic performance
and a 250 MHz Full Power Bandwidth. Operating on a single
+3.0V power supply, the ADC12DL040 achieves 11.1 effec-
tive bits at nyquist and consumes just 210 mW at 40 MSPS,
including the reference current. The Power Down feature
reduces power consumption to 36 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
REF
with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADC’s are available on a single multiplexed 12-bit
bus or on separate buses. Duty cycle stabilization and output
data format are selectable using a quad state function pin.
The output data can be set for offset binary or two’s comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL040 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evalua-
tion process.
Features
n Single +3.0V supply operation
n Internal sample-and-hold
n Internal reference
n Outputs 2.4V to 3.6V compatible
n Power down mode
n On-chip reference
n Duty Cycle Stabilizer
n Multiplexed Output Mode
Key Specifications
n Resolution 12 Bits
n DNL ±0.3 LSB (typ)
n SNR (f
IN
= 10 MHz) 69 dB (typ)
n SFDR (f
IN
= 10 MHz) 85 dB (typ)
n Data Latency 7 Clock Cycles
n Power Consumption
n -- Operating 210 mW (typ)
n -- Power Down Mode 36 mW (typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
Connection Diagram
20100201
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
February 2005
ADC12DL040
Dual
12-Bit,
40
MSPS,
3V
,
210mW
A/D
Converter
© 2005 National Semiconductor Corporation DS201002 www.national.com