Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. A
03/24/04
IS65C256 ISSI
®
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this speci fication and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FUNCTIONAL BLOCK DIAGRAM
32K x 8 LOW POWER CMOS
STATIC RAM
FEATURES
• High-speed access time: 20 ns
Low active power: 200 mW (typical)
Low standby power:
250 µW (typical) CMOS standby
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V power supply
Temperature Offerings:
Option A1: –40
o
C to +85
o
C
Option A2: –40
o
C to +105
o
C
Option A3: –40
o
C to +125
o
C
MARCH 2004
DESCRIPTION
The ISSI IS65C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-
performance, low power CMOS technology.
When CS is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Select (CS) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS65C256 is Packaged in the JEDEC Standard 28-Pin
SOP and 28-Pin TSOP (Type I).
A0-A14
CS
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7