AD9953
器件描述：400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer
器件厂商：AD [Analog Devices]
文件大小：473.2KB，共42页
Sponsor by e络盟器件资料摘要：
A
400 MSPS 14-Bit, 1.8V CMOS
Direct Digital Synthesizer
Preliminary Technical Data AD9953
REV. PrB 1/30/2003
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved.
FEATURES
400 MSPS Internal Clock Speed
Integrated 14-bit D/A Converter
Programmable phase/amplitude dithering
32-bit Tuning Word
Phase Noise <= -125 dBc/Hz @ 1KHz offset (DAC output)
Excellent Dynamic Performance
80dB SFDR @ 130MHz (+/- 100KHz Offset) Aout
Serial I/O Control
1.8V Power Supply
Software and Hardware controlled power down
48-lead EPAD-TQFP package
Linear and non-linear frequency sweeping capability
Integrated 1024x32 word RAM
Support for 5v input levels on most digital inputs
PLL REFCLK multiplier (4X to 20X)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multi-Chip Synchronization
APPLICATIONS
Agile L.O. Frequency Synthesis
FM Chirp Source for Radar and Scanning Systems
Automotive Radar
Test and Measurement Equipment
PSK/FSK/Ramped FSK modulation
Functional Block Diagram
DAC
DAC
I-set
Aout
Aout
System Clock
Timing & Control Logic
I/O
Update
RefClk
Sync
Out
IO Port
Control Registers
Sy
n
c
Reset
M
U
X
4x-20x Clock
Multipler
System Clock
RefClk
Oscillator/Buffer
SYNC
0
4
M
U
X
Phase
Accumulator
COS(x)
Phase
Offset
DDS Core
19
z
-1
Σ Σ
z
-1
DDS Clock
PS<1:0>
OSK
PwrDwn
Static RAM
1024 x 32
32
10
3
32
RAM
Data
M
U
X
14
θ
M U X
RAM Data <31:18>
32
32
32
14
32
Crystal
Out
ENABLE
14
Ph
ase
A
c
c
u
mu
l
a
t
o
r
R
ESE
T
Fr
equ
e
n
cy
T
unin
g
Wor
d
DD
S
C
l
o
c
k
RAM
C
ont
rol
RA
M
A
dd
r
RAM
D
a
t
a
400 MSPS 14-Bit, 1.8V CMOS
Direct Digital Synthesizer
Preliminary Technical Data AD9953
REV. PrB 1/30/2003
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved.
FEATURES
400 MSPS Internal Clock Speed
Integrated 14-bit D/A Converter
Programmable phase/amplitude dithering
32-bit Tuning Word
Phase Noise <= -125 dBc/Hz @ 1KHz offset (DAC output)
Excellent Dynamic Performance
80dB SFDR @ 130MHz (+/- 100KHz Offset) Aout
Serial I/O Control
1.8V Power Supply
Software and Hardware controlled power down
48-lead EPAD-TQFP package
Linear and non-linear frequency sweeping capability
Integrated 1024x32 word RAM
Support for 5v input levels on most digital inputs
PLL REFCLK multiplier (4X to 20X)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multi-Chip Synchronization
APPLICATIONS
Agile L.O. Frequency Synthesis
FM Chirp Source for Radar and Scanning Systems
Automotive Radar
Test and Measurement Equipment
PSK/FSK/Ramped FSK modulation
Functional Block Diagram
DAC
DAC
I-set
Aout
Aout
System Clock
Timing & Control Logic
I/O
Update
RefClk
Sync
Out
IO Port
Control Registers
Sy
n
c
Reset
M
U
X
4x-20x Clock
Multipler
System Clock
RefClk
Oscillator/Buffer
SYNC
0
4
M
U
X
Phase
Accumulator
COS(x)
Phase
Offset
DDS Core
19
z
-1
Σ Σ
z
-1
DDS Clock
PS<1:0>
OSK
PwrDwn
Static RAM
1024 x 32
32
10
3
32
RAM
Data
M
U
X
14
θ
M U X
RAM Data <31:18>
32
32
32
14
32
Crystal
Out
ENABLE
14
Ph
ase
A
c
c
u
mu
l
a
t
o
r
R
ESE
T
Fr
equ
e
n
cy
T
unin
g
Wor
d
DD
S
C
l
o
c
k
RAM
C
ont
rol
RA
M
A
dd
r
RAM
D
a
t
a