1
Data sheet acquired from Harris Semiconductor
SCHS140E
Features
• Asynchronous Set and Reset
• Schmitt Trigger Clock Inputs
• Typical f
MAX
= 54MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Pinout
CD54HC109, CD54HCT109
(CERDIP)
CD74HC109, CD74HCT109
(PDIP, SOIC)
TOP VIEW
Description
The ’HC109 and ’HCT109 are dual J-K flip-flops with set and
reset. The flip-flop changes state with the positive transition
of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S and R,
respectively. A low on both the set and reset inputs
simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously
results in an unpredictable output condition.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1R
1J
1K
1CP
1S
1Q
GND
1Q
V
CC
2J
2K
2CP
2S
2Q
2Q
2R
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC109F3A -55 to 125 16 Ld CERDIP
CD54HCT109F3A -55 to 125 16 Ld CERDIP
CD74HC109E -55 to 125 16 Ld PDIP
CD74HC109M -55 to 125 16 Ld SOIC
CD74HC109MT -55 to 125 16 Ld SOIC
CD74HC109M96 -55 to 125 16 Ld SOIC
CD74HCT109E -55 to 125 16 Ld PDIP
CD74HCT109M -55 to 125 16 Ld SOIC
CD74HCT109MT -55 to 125 16 Ld SOIC
CD74HCT109M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
March 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC109, CD74HC109,
CD54HCT109, CD74HCT109
Dual J-K Flip-Flop with Set and Reset
Positive-Edge Trigger
[ /Title
(CD74H
C109,
CD74H
CT109)
/Subject
(Dual J-
K Flip-
Flop
with Set
and
Reset